Path-balanced logic design to realize block ciphers resistant to power and timing attacks

Abstract

In this paper, binary decision diagram (BDD)-based dual-rail precharge logic circuit schemes have been developed to counter differential power analysis attacks, timing attacks, and early propagation attacks. Different precharge logic schemes (top precharging, top-bottom precharging, bottom precharging, and symmetric nMOS bottom precharging) are presented and evaluated. The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realize the required Boolean function. A simple synthesis algorithm..